DC_Compiler timing constraint

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eng_ahmed_osama

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how i can put timing constraint to each path in design i am using DC_compiler , when i synthesize it gives me a slack zero all the time and in the timing report their is a notification that path is unconstrained
 

there is no need to make all paths to constrained.
By functional or case analysis statement based, few paths are not active arcs ( means no logic transition is going to happen in that path )
 

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