DC voltage rejection?

[khorramrouz]

although i change Vgs and W/L ratio, when i set the input to zero, a dc voltage is seen at output node. how can i reject this and what is it,s reason?
thanks for your help

 

[kemiyun]

I think you should explain more. If you set the input to zero and turn off an NMOS device and if nothing else is connected to that node, you would definitely see some voltage there. The question is, is this something you wanted? If you want that node to go to a predetermined voltage you can switch the output to that voltage. Or if you deliberately wanted to make a net floating you should make sure that the floating net stays withing acceptable voltage range.

 

[dick_freebird]

Input offset voltage, finite gain error, load current voltage rise?

How about you offer any description at all of the circuit and
its close-in environment / application?

 

[khorramrouz]

Dear friend
the question is about an folded cascode OTA with single ended output.to have good swing i designed the circuit and set Vbias and W/L ratio. Vdd=1 v and Vss=-1v. under this condition a dc voltage (407 mv) seen at output node which eleminates the + swing. so i want to know :
1-how much should be the DC voltage at output node?
2-this dc voltage is Common mode voltage or offset or my designing have some mistakes?
3-i want to buffer this OTA with a Push-pull source folloer, and this dc voltage influence on the buffer biasing.
best regards

 

[nitishn5]

With the very vague information provided, it seems that you have a biasing issue.

I am guessing that while you expect that the OTA output should be at 0V with no input, but you get the 407mV.

If this is true, it is unlikely that this is some offset but there some mistake in the design.

Show your schematics and specifications.
How are you biasing the circuit? Do you have a biasing circuit?

Do you have an input common mode voltage?