Agreed that it will not automatically tie a floating input; but to my knowledge it will not remove it as well.
Usually it leaves it in the verilog with SYNOPSYS_UNCONNECTED_ also I do not think it should play with the module definitions
From my knowledge the port input cannot be removed as well as not tied to any value. Lint toll or synthesis tool generally use to theow warnings on unconnected input/output port. If the input is just declared and not logically used, then this warning can be waived. else proper care should be given to tie the input/feed the input.