Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Agreed that it will not automatically tie a floating input; but to my knowledge it will not remove it as well.
Usually it leaves it in the verilog with SYNOPSYS_UNCONNECTED_ also I do not think it should play with the module definitions
From my knowledge the port input cannot be removed as well as not tied to any value. Lint toll or synthesis tool generally use to theow warnings on unconnected input/output port. If the input is just declared and not logically used, then this warning can be waived. else proper care should be given to tie the input/feed the input.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.