DC Synthesis constraints Vs PT STA Constraints

[analog_fever]

Just want to know the opinion of the forum. Is it preferred to use exactly the same set of constraints for both synthesis using DC, and STA using PrimeTime?

Does the synthesis tool use the false path specifications, or max transition constraints?

Or can we use a simpler constraint file to do synthesis, and then use a more elaborate constraint file for STA?

 

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Back when I was working on ASICs the false path specification would be used by DC to not try any timing optimizations to improve that path. The max transitions would result in DC beefing up the drivers used if the path had a large number of loads. Don't know if there have been improvements on the wire models to be more conservative. I remember we had issues with the models being a little to optimistic.