dc gain in pole zero simulation

[vasantiitm]

In cadence pole zero simulation gives constant factor and dc gain.
but the dc gain what i get is not same as the dc gain obtained using calculator at the output node. pls tell me why both are not same?

 

[saro_k_82]

I hope you are calculating the open loop gain and simulating for the closed loop gain

 

[vasantiitm]

hi thank u for the response. I have calculated the dc gain for the closed loop still is not matching with what i get in cadence calculator response. Can u pls help in this regard

 

[saro_k_82]

This sounds strange. Are you sure that you have all transistor stages work in proper bias regions and the loop stability margins are good enough?
Aside this, what is important are the locations of the open loop poles and zeros for selecting the right compensation method and the compensating network. After compensation, the closed loop pole locations (Zeros are uninteresting) should be first or second order which does not "give" much unlike the closed-loop step transient response. So you have to find the dc gain and the pole, zero locations of the open-loop response.