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Data required on how IR-Drop analysis done at block level.

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qual_ti

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Hi,


I need some information how IR-Drop analysis is done at block level and what the things effect the IR-Drop .

Which tool can be used to analyze the IR-Drop at block level.At what stage we have to do his.

I need information what IR-Drop and how it effect our chip etc.

I hope u will help me in this regard

Thanks in advance.
 

yadavvlsi

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IR drop refers to voltage drop in power distribution interconnect lines in a chip which can be static or dynamic. This can voltage drop hence reducing supply voltage reaching to the standard cell. So standard cell will not work properly.

Static IR drop
Static IR drop are drop in VDD voltage level caused by the resistance of the metal wires comprising the power distribution. In other words it is a drop due to current flow through the interconnect lines when the circuit is at a steady state i.e. no inputs are switching. The factor affecting the static IR drop are basically the dimensions of power rails(widths, vias,etc), power switch sizes.

Dynamic IR drop
Dynamic IR drops refers to the voltage drop in VDD due to current flowing when the circuit is switching. It occurs at the active edge of the clock when the simultaneous switching of on-chip components such as clocks, clocked elements, bus drivers and memory decoder drivers occurs. This simultaneous switching draws a high current from the power grid for a very small duration.

Affect of IR drop in design
If the source of power is very far from a flip flop seeing dynamic IR drop , that flop might have metastability issues. Typically, high IR drop on clock networks causes hold-time violations, while IR drop on signal nets causes setup_time violations. Every design suffers IR drop, so, the question is not how to avoid IR drop but to minimize so that there is no timing or signal integrity noise issues in design.

IR drop analysis
Understanding these IR drops is vital in power efficient design. There is no fixed relationship between static and dynamic IR drop in a design. Dynamic IR drop are independent of frequency whereas static IR drop vary with clock frequency. These IR drops in various areas in chip can be known from power rail analysis. It is imperative in todays design to do power analysis early in the design and fix any power issues along the flow. This will avoid last minute costly modification to fix power issues.

Tools used:
Voltagestrom from is cadence is used to show IR drop on chip. It is available as of Encounter.
https://www.cadence.com/products/di/voltagestorm
https://www.cadence.com/rl/Resources/datasheets/voltage_storm_ds.pdf
Search for "voltagestorm" in google you will get enough details.
 

gaurav_sharma

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Redhawk by Apache is also good to estimate Static and Dynamic voltage drop analysis.
 

design_oriented

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"Dynamic IR drop are independent of frequency whereas static IR drop vary with clock frequency. "

Do you mean to say the opposite of the above?

Apache Redhawk is a much better graphical tool for IR drop analysis.
 

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