Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

data rate of a design in fpga implementation

Status
Not open for further replies.

max420

Newbie level 5
Newbie level 5
Joined
Nov 30, 2010
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,358
hi i find it on a project report "spartan 2e 1339 LUTs (87%),88MHz" how to find the data rate of a design with xilinx/altera software?please help.thanks in advance
 

Without knowing what the design is, you have no idea.
 

hi i find it on a project report "spartan 2e 1339 LUTs (87%),88MHz" how to find the data rate of a design with xilinx/altera software?please help.thanks in advance

Here is the general process: You implement the design preferably with some timing constraints in Xilinx or Altera implementation tools. You will get a report in the end showing how fast the design will run.
 

that wont show you the data rate, that will just show you the clock speed.

If the clock speed is 100Mhz, but the design only outputs a value once every 4 clocks, the data rate would be 25Mwords/s
 

that wont show you the data rate, that will just show you the clock speed.

If the clock speed is 100Mhz, but the design only outputs a value once every 4 clocks, the data rate would be 25Mwords/s

Good point. Since the OP mentioned "spartan 2e 1339 LUTs (87%),88MHz", I assumed he asked about clock speed.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top