data rate of a design in fpga implementation

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max420

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hi i find it on a project report "spartan 2e 1339 LUTs (87%),88MHz" how to find the data rate of a design with xilinx/altera software?please help.thanks in advance
 

Without knowing what the design is, you have no idea.
 

max420 said:
hi i find it on a project report "spartan 2e 1339 LUTs (87%),88MHz" how to find the data rate of a design with xilinx/altera software?please help.thanks in advance
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Here is the general process: You implement the design preferably with some timing constraints in Xilinx or Altera implementation tools. You will get a report in the end showing how fast the design will run.
 

that wont show you the data rate, that will just show you the clock speed.

If the clock speed is 100Mhz, but the design only outputs a value once every 4 clocks, the data rate would be 25Mwords/s
 

TrickyDicky said:
that wont show you the data rate, that will just show you the clock speed.

If the clock speed is 100Mhz, but the design only outputs a value once every 4 clocks, the data rate would be 25Mwords/s
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Good point. Since the OP mentioned "spartan 2e 1339 LUTs (87%),88MHz", I assumed he asked about clock speed.
 

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