fuccx2000
Newbie level 1
Design a data path and a controller to repeatedly receive characters in 7-bit odd parity format (i.e., the parity bit is 1 if the number of ones in a given set of bits is even). The bits are received synchronously, i.e., one bit per clock. The most significant data bit (MSB) is received first, with the parity bit received last. The first bit is the bit received after the receiving two consecutive zero bits. The end bit is always a logic 1, and the data stays high until the start bits are received.
An example of the data stream is shown below:
… 1 1 1 1 1 0 0 d6 d5 d4 d3 d2 d1 d0 parity 1 0 0 d6 d5 …
When receiving the end character, the seven data bits should be transferred in parallel to the data output port. If there is a parity error, the output port ERROR should be asserted high (low if otherwise).
Draw the registers and logic blocks as a schematic, as well as the controller state machine state diagram. Write the VHDL code to implement the controller state machine. Your codes should be parameterized, such that the machine is able to support 7-bit or 8-bit characters, based on the value in the input port LENGTH.
Is there anbody can help this problem? I don't what to do at all. Thank u guys!
An example of the data stream is shown below:
… 1 1 1 1 1 0 0 d6 d5 d4 d3 d2 d1 d0 parity 1 0 0 d6 d5 …
When receiving the end character, the seven data bits should be transferred in parallel to the data output port. If there is a parity error, the output port ERROR should be asserted high (low if otherwise).
Draw the registers and logic blocks as a schematic, as well as the controller state machine state diagram. Write the VHDL code to implement the controller state machine. Your codes should be parameterized, such that the machine is able to support 7-bit or 8-bit characters, based on the value in the input port LENGTH.
Is there anbody can help this problem? I don't what to do at all. Thank u guys!
