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Data missing with FT2232D in DLP FPGA

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digitalforfun

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Hello,
I am using DLP FPGA kit which contains FT2232D chip. Data transfer is through parallel FIFO interface and D2xx driver. I have to transfer 3 bytes of data with different data rate.This 3 bytes of data is generated at X/Y rate in FPGA . Here X can have value of 5MHz, 7.5Mhz, 10 Mhz, 15MHz or 20 Mhz and Y will have value 256, 128 or 64.

But while reading through application i am seeing data corruption in few samples. Earlier i was using Driver CDM 2.04.6 in which many samples were getting corrupted. In the application i had Settimer which has counter of 100 ms.So continuously every 100 ms i was reading the samples . To avoid the data corruption in the application i used to Reset after reading 20480 bytes using command "FT_ResetDevice".But even in this 20480, first 750 samples will be corrupted .but always For option X/64 and X/128 data was corrupted after 10240 samples

main()
{ SetTimer(15,100, NULL)}


void CCStatsDlg::OnTimer(UINT nIDEvent)
{
status = GetQueueStatus(&bytes_in_buf);
if(bytes_in_buf)
{
status = Read(rx, bytes_in_buf<20480 ? bytes_in_buf : 20480, &ret_bytes);
if((status == FT_OK) || ((status == FT_IO_ERROR) && (ret_bytes > 0)) /* Read timeout */)
{
if(ret_bytes)
{
UpdateData(TRUE);

for(DWORD x=0; x<20480; x++)
{
if(rx[x] == 0xff)
{

temp_output= 64*rx[x+2]+rx[x+1];
fprintf(fp_write,"%d\n",temp_output);
}

Now i have upgraded the driver to CDM2.08.14 .Now data corruption is less frequent but still present.

The state machine for TXE and RXF in FPGA looks ok for me. So not sure what is the problem..

Any suggestion?
 

alexadmin

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Does you check busy status from FTDI chip in FPGA? It is need to analyze when FPGA perform writing to FTDI, but FTDI sets busy at the same clock cycle. Also you need to set flow control for Synchronous FIFO mode in software.
 

digitalforfun

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Hello alexadmin,

Thanks for your reply.

In FPGA if txe goes low, then only data is sent. I think if FTDI chip is busy the txe will be high. So can you please elaborate how it can be busy at the same clock cycle

Can you please explain what you are trying say below
"set flow control for Synchronous FIFO mode in software"
Are you telling read operation in software. How to set the flow control?

Can you explain this to me ?

Thanks in advance.
 

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