dtn_me
Junior Member level 3
PCIe Phy
Hi
I am doing PCIe physical layer verification. For Gen1 and Gen2, PCIe transmits 20 bit data and receives 16 bit data. I am in the process of bulding up a test bench environment for this.
I am actually preparing an expected data buffer. This is 16 bit buffer. Need to take 16 bits from the 20-bit data packet. The 4 bits remaining will be received in the next data packet. Can anybody tell me the working logic for this? I have been thinking for a logic but still not marked.
Please suggest.
Hi
I am doing PCIe physical layer verification. For Gen1 and Gen2, PCIe transmits 20 bit data and receives 16 bit data. I am in the process of bulding up a test bench environment for this.
I am actually preparing an expected data buffer. This is 16 bit buffer. Need to take 16 bits from the 20-bit data packet. The 4 bits remaining will be received in the next data packet. Can anybody tell me the working logic for this? I have been thinking for a logic but still not marked.
Please suggest.