Data buffer for PCIe physical layer verification

[dtn_me]

PCIe Phy

Hi

I am doing PCIe physical layer verification. For Gen1 and Gen2, PCIe transmits 20 bit data and receives 16 bit data. I am in the process of bulding up a test bench environment for this.

I am actually preparing an expected data buffer. This is 16 bit buffer. Need to take 16 bits from the 20-bit data packet. The 4 bits remaining will be received in the next data packet. Can anybody tell me the working logic for this? I have been thinking for a logic but still not marked.

Please suggest.

 

[FvM]

Re: PCIe Phy

I basically don't understand your bit counting. At physical layer, PCIe (as other fast serial protocols, e. g. Ethernet or SATA) transmits and receives 8-Bit entities using 8b/10b coding/decoding. What is a 20-bit data packet in this regard?