Maybe you have the PDK for a related, but not proper,
flow-variant (like, "plain digital" low cost flows might
omit the MIM steps to save a fractional penny per die).
You can get gross MIM scatter from PCM specs although
these are "sandbagged", you could get them from a
foundry modeling report / document if you asked nicely
and signed / paid as necessary. The mismatch stuff will
not appear in production test data almost certainly.
You can pretty much assume that 14 bits is not going
to happen without error correction or trimming or both,
in this style of DAC.
You might, in the absence of data, assert some range
of capacitor mismatch at the size in question (itself,
a modeling chore that may or may not have led to
realistic L, W, area dependences of mismatch in the
model). Say, run at 0.01%, 0.1%, 1% mismatch (use
a gaussian multiplier to the base C value expression)
and may as well use an analogLib capacitor as you
are not asking about systematic variation. You could
of course also make the generic C value include other
variables.