CML is certainly not neccessary, reasonable (<say sub 1024 division ration) freq. dividers can easily be built out of plain vanilla CMOS logic and standard master slave flops and work at 800MHz even in 0.18, not to mention 0.13.
CML might have advantages in the dividers if you are after extremely low jitter and your loop BW is is very low since it is a very low noise topology (almost no switching noise since it always sinks the same current, even during value changes, this makes it very high power though).