[SOLVED] D-Algorithm for test pattern generation

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guru2kiot

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Hello,
For generate test patterns how to apply d-algorithms/podem algorithms steps using verilog??

Please can anyone tell me the procedure how to apply d-algorithms process using verilog???
 

Using Verilog..........really?

Which ATPG tool are you using?
As far as I know, you have to specify the algo name (along with other necessary parameters) and the tool o/p the patterns for you (generally one writes a script which is input to the ATPG tool).
I would ask you to refer to the user guide your ATPG tool.
 
Hello dpaul,
Thank you very much for your valuable response......yes for generating test patterns, D-algorithm/podem algorithm steps by using verilog.
and till now I am not used ATPG tools...I am planning to use ATPG tools...but before going use ATPG tools,need to simulate D-algorithm/podem algorithm in verilog...so if you known how to apply the steps in verilog please share...
 

I have never generated test-patterns at the test-bench level (functional/behavorial simulation stage). The use of tool-generated test-patterns comes in after DFT insertion. What you have mentioned doesn't sound like standard flow to me (correct me if I am wrong). It is best to leave it to the ATPG tool else I guess there is huge complexity.

When I was working with ASICs, I had used ATPG tool (and had configured it to use a particular algo) to generate test-patters to be used by the MBIST engines. It would have been too complex for a Verilog test-bench to generate all those test-patterns which an ATPG tool does.
 
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