Current control for depletion FET

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padpan

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Hi,

I am designing a PA using self-biased configuration. The CS device is a depleted FET whose Vth may become negative over FAST process corner (even if the Vgs of the driver of the current mirror is zeroed the CS device will still be conducting significant current). Could anyone suggest a way to effectively control the current passing through the CS device?

Thanks in advance,
padpan
 

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