[SOLVED] Critical path timing (Synopsys DC)

[dirac16]

I'm trying to synthesize a multi-input multi-output digital circuit formed by combinational blocks. As there are various input-output paths we would have many paths to worry about their propagation delay. So how to globally constrain the critical path to within a max value?

 

[KlausST]

Hi,

This is one reason why a "clocked system" is preferred.
May I ask why you want it to be combinatorial?

Klaus

 

[dirac16]

Hi,

This is one reason why a "clocked system" is preferred.
May I ask why you want it to be combinatorial?

Klaus

I'm just synthesizing a behavioral HDL circuit. The circuit is simply an 8b adder followed by a 13b multiplier (it multiplies the output of the adder by a fix number). So I don't see how it could be a clocked system?

 

[KlausST]

Hi,

You have a standa4d system:
Input --> processing --> output

An input has a "time where it changes state" (invalid) and a "time where the state is valid and stable"
This needs to be defined somehow. In many cases these states are related to a clock...indeed it depends on the source of the information.
Maybe it's a microcontroller, maybe a counter...maybe something else.
We don't know what this is in your case.
--> but you need to define somehow "when" your input is valid.

Then there is the processing unit.
As long as the input is invalid .. you may process the data or not, but the result will be invalid.
So beginning with the point of time where the input is considered as valid .... your processing unit needs some time to get stable outputs.
In your case there will be a worst case path from "input LSB" to "output MSB" (maybe you have additional inputs or outputs like: zero_flag, carry_flag, ...)

The output then is valid when:
* input was and still is valid
* and after the timing of the worst case path.

Clocked systems makes it more simple to define "valid" and "invalid" timing, because you have a reference "time" to refer to.
"Rising clock edge" for example.

And for sure an adder or a multiplier can be clocked .... or pipelined.

****
Try to define when input and output data is considered "valid".

Klaus

 

[dirac16]

Hi,

You have a standa4d system:
Input --> processing --> output

An input has a "time where it changes state" (invalid) and a "time where the state is valid and stable"
This needs to be defined somehow. In many cases these states are related to a clock...indeed it depends on the source of the information.
Maybe it's a microcontroller, maybe a counter...maybe something else.
We don't know what this is in your case.
--> but you need to define somehow "when" your input is valid.

Then there is the processing unit.
As long as the input is invalid .. you may process the data or not, but the result will be invalid.
So beginning with the point of time where the input is considered as valid .... your processing unit needs some time to get stable outputs.
In your case there will be a worst case path from "input LSB" to "output MSB" (maybe you have additional inputs or outputs like: zero_flag, carry_flag, ...)

The output then is valid when:
* input was and still is valid
* and after the timing of the worst case path.

Clocked systems makes it more simple to define "valid" and "invalid" timing, because you have a reference "time" to refer to.
"Rising clock edge" for example.

And for sure an adder or a multiplier can be clocked .... or pipelined.

****
Try to define when input and output data is considered "valid".

Klaus

I understand. The thing is that I don't care about input valid time. The inputs change every 50ns. In other words, the time at which input data change is not certain, but can be anything from 0 to 50ns. Considering that the critical path is no more than 10ns, defining an input (output) valid time is not necessary for my design. If the inputs were likely to change at any time, then your points are right and inputs and outputs must be timed with a clock. So still do you recommend a clocked design?

 

[KlausST]

Hi,

if you don´t care about "valid time", then:
To me this means you don´t care about of the rest of the time = the "invald_time".
So you don´t care about "validity" at all.

You never know at which point of time the input is valid ... thus it´s impossible to know when the output is valid.
--> don´t care about the propagation time. The output "never" can be considered as valid.
Or in "my words": The circuit (output) is not reliable ... thus the circuit is useless.

I guess you want to disagree ;-)
Then please explain. Maybe draw a timing diagram..

"explain" and "timing diagram" are some kind of specifications. And specifications are key to a reliable system:

Example1:
Is a thermometer with a tolerance of +/-2°C good or not?
* for a smith, working at around 900°C a tolerance of +/-2°C is more precise than needed
* for a doctor a thermometer with +/-2°C is crap.

Example2:
Designing a room temperature controller to regulate the room temperature to exactly 22°C will (practically) fail, because it tries to heat up to 22.00°C, then a millisecond later it tries to cool down. Heating and cooling will kill each other. --> One needs a useful timing and one needs useful temperaure thresholds.
Maybe simply: one decision per 5 minutes. Below 21°C --> heating, above 23°C cooling, inbetween --> nothing.

Klaus

 

[dirac16]

Hi,

if you don´t care about "valid time", then:
To me this means you don´t care about of the rest of the time = the "invald_time".
So you don´t care about "validity" at all.

You never know at which point of time the input is valid ... thus it´s impossible to know when the output is valid.
--> don´t care about the propagation time. The output "never" can be considered as valid.
Or in "my words": The circuit (output) is not reliable ... thus the circuit is useless.

I guess you want to disagree ;-)
Then please explain. Maybe draw a timing diagram..

"explain" and "timing diagram" are some kind of specifications. And specifications are key to a reliable system:

Example1:
Is a thermometer with a tolerance of +/-2°C good or not?
* for a smith, working at around 900°C a tolerance of +/-2°C is more precise than needed
* for a doctor a thermometer with +/-2°C is crap.

Example2:
Designing a room temperature controller to regulate the room temperature to exactly 22°C will (practically) fail, because it tries to heat up to 22.00°C, then a millisecond later it tries to cool down. Heating and cooling will kill each other. --> One needs a useful timing and one needs useful temperaure thresholds.
Maybe simply: one decision per 5 minutes. Below 21°C --> heating, above 23°C cooling, inbetween --> nothing.

Klaus

Believe me it works without clocking. The system is part of a larger system. The outputs need to be sampled by clock ACLK, where ACLK arrives always much later than input data + critical delay. That means outputs are already valid at the time sampled by ACLK. That also means whenever inputs are invalid the outputs are not needed. This is kind of a pseudoclocked system.

 

[KlausST]

Hi,

I never did say it does not work.

Just my opinion: If you have a circuit and you never know "when" your output is valid, then it is unreliable .. and an device with unreliable output, I call "useless".

****
Indeed the discussion is not about "functional or not", it is about the missing timing information.

Imagine a railway gate. It does "work" when it goes up and down. But it is "useless" when it goes up and down at the wrong time. --> The timing needs to be referenced to the train.

****
And now there is ACLK . Hooray! We have a reference for the timing!

ACLK arrives always much later ..."

we never had this information before. Urgent information.

--> this is the missing specification that defines when the data is valid or not... and thus whether a circuit is useless or not. (see my second post)

But

always much later

... is meaningless without a value. It may be picoseconds .. it may be half a year.
This exactly now is your job to find out how input_data and output_data need to be related to ACLK.
I guess no one of us can do this for you.
This is how your timing has to constrained.

That also means whenever inputs are invalid the outputs are not needed.

This is what a timing diagram is for....

***


Klaus

 

[dirac16]

... is meaningless without a value. It may be picoseconds .. it may be half a year

Sorry, it was my fault to hide vital information. The arrival time of ACLK is at least 5ns later so it meets output timing specification.

My question was more of a synthesis issue where I don't know how to deal with constraining critical path. My solution was to use set_max_delay delay_value -from {input_port} -to {output_port} to impose a max limit on the critical path. The problem with this approach is that it does not consider the second, third, etc. longest critical paths in the optimization. What generally do you do when trying to optimize the design for the lowest possible propagation delay? Lets say we don't care much about area and power for simplicity.

 

[KlausST]

Hi,

I´m a bit confused now.
If you are constraining input_port to output port then it should work.
.. for the fastest path (like LSB to LSB)
.. and for the slowest path (like LSB to MSB)

And if the longest critical path meets this requirement then all others should do also.

Klaus

 

[dirac16]

If you are constraining input_port to output port then it should work.
.. for the fastest path (like LSB to LSB)
.. and for the slowest path (like LSB to MSB)

Thank you so much! It's working now. First time I tried to constrain both input-output path of the adder and multiplier individually. It didn't work. Now it worked when I assigned LSB input to the start_point and MSB output to the end_point. It's beautiful! Just one question, how could you guess the slowest path is from LSB input to MSB output? I didn't not show you the circuit?

 

[KlausST]

Hi,

Guess you have 0b11111111 then add 0b00000001
You have to add the LSBs first, then the carry ripples through all (1, 2, 3, ...) bits to the MSB, this is the longest path.

Klaus