Definately size of PMOS is 3 times larger than NMOS.
So mobilty is 1/3 of NMOS.
iIn General Crital Path is largest distance frm I/P to O/P, Reg to O/P,Reg to Reg.,I/p to Reg.You need to reduce the Critical Path by including FF.
Hi..
As I understand question was regarding PMOS size in SRAM cell.
As PMOS size is decreased in SRAM the stability of SRAM cell decreases.
As per the critical path in SRAM I would suggest that it is not straight forward.
There are 2 paths which are in race.
1.. Clock to Row Selection
2. Clock to Precharge switch off.
So, the path which constitutes more delay will be Critical path in this case.
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hi nitu,
wat i said before is the universal concept,.
The critical path in an SRAM is the Read Operation. The bit line has to be discharged thro 2 transistors in series. Devices have to be sized to prevent the intermediate node from charging up too much. For the write operation, all constraints are automatically met by a large margin.
CRITCAL PATH determines the max. freq of operation.:idea: