critical path in SRAM

[kumar_eee]

What’s the critical path in a SRAM?

 

[ericyuan]

read or write?

 

[kumar_eee]

Can you please explain for both?.

 

[gcreddy]

A friend of mine was asked this question during an interview with Qualcomm. Though he didn't get it, the interviewer explained him the answer which is as follows:

A Critical path in the SRAM is activated when a logic 1 is read from the cell at the first row's last column. This constitutes the critical path because when the word line is asserted from the row decoder, it has to charge ALL the gates of the pass transistors preceding the final column before the final column's pass transistors are asserted high. Likewise, after this process, when a 1 is read from this cell, it has to charge all all the parasitic capacitors in the entire column before charging the read / write buffer input.

Likewise, there exists a critical for a write operation with certain riders which I do not remember precisely. You can figure it out by yourself if you think about the write operation on the previous lines.

Thank you.

 

[kumar_eee]

@gcreddy, Thanks alot..