Creating clock with multiple edges in RTL compiler

[rakeshbabugr]

Hi,

I've seen that in RTL compiler, we cannot use the create_clock with more than two edges in the clock waveform. But, there seems to be this option in Synopsys DC. I see that this limitation is a problem with designs have non-free running clocks like SCLK in SPI interface. It complicates the timing constraints especially if there are lots of false paths.
How have you guys overcome this issue when using RTL compiler?

Syntax for create_clock for RTL compiler:
create_clock
[-add]
[-name clock] [-domain clock_domain]
-period float [-waveform float]
[-apply_inverted {port|pin}]
[port|pin] [-comment string]

Syntax for create_clock for Synopsys Design compiler:

create_clock
[-name clock_name] [-add] [source_objects] [-period period_value] [-waveform edge_list] [-comment comment_string]

 

[jt_eaton]

Just because you call it a clock doesn't mean that it is a clock. If your internal free running clock is fast enough then you sample the SCLK signal and use it as a data signal. All of your timing comes from your internal clock