Creating clock based on a signal's state change

[miroseh]

Hi all,
We have the signal clk_27mhz on DE2 board. But I want to create a different clock signal to be implemented as a clock for a shift register.

Q ________----------------_________ (period in seconds)
clk _______--____________--_______ (active high in microseconds, eg 5us)

Could you give me some suggestion? Thank you.

 

[BradtheRad]

You wish to create a series of pulses independent of the clock.

1. It goes high when the clock goes high.

2. Waits a miniscule time.

3. Returns to low.

4. Stays low for 80 percent of the time the clock is high.

5. Returns to high.

6. Clock goes low.

======================

The obvious way is with two one-shot timers.

For the first one, there's an easy way to arrange a capacitor, resistor and diode so that output drops back to low soon after it goes high.

Feed it to the trigger of one-shot #2.

You adjust the one-shot manually to hold low for a set period.

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Excuse me, now I see I neglected to include a way for the second signal to return low when the clock goes low.

 

[FvM]

You would want to implement a state machine respectively synchronous edge detection logic and a counter, operated with the 27 MHz system clock.

The obvious way is with two one-shot timers.

There are other obvious ways for it in FPGAs (programmable logic). If you don't know what DE2 is (an Altera FPGA development board), you should notice the forum.