Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Creating clock based on a signal's state change

Status
Not open for further replies.

miroseh

Newbie level 2
Joined
Dec 6, 2010
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,300
Hi all,
We have the signal clk_27mhz on DE2 board. But I want to create a different clock signal to be implemented as a clock for a shift register.

Q ________----------------_________ (period in seconds)
clk _______--____________--_______ (active high in microseconds, eg 5us)

Could you give me some suggestion? Thank you.
 
Last edited:

BradtheRad

Super Moderator
Staff member
Joined
Apr 1, 2011
Messages
14,226
Helped
2,814
Reputation
5,636
Reaction score
2,754
Trophy points
1,393
Location
Minneapolis, Minnesota, USA
Activity points
106,128
You wish to create a series of pulses independent of the clock.

1. It goes high when the clock goes high.

2. Waits a miniscule time.

3. Returns to low.

4. Stays low for 80 percent of the time the clock is high.

5. Returns to high.

6. Clock goes low.

======================

The obvious way is with two one-shot timers.

For the first one, there's an easy way to arrange a capacitor, resistor and diode so that output drops back to low soon after it goes high.

Feed it to the trigger of one-shot #2.

You adjust the one-shot manually to hold low for a set period.

------------------------------------

Excuse me, now I see I neglected to include a way for the second signal to return low when the clock goes low.
 
Last edited:

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
49,116
Helped
14,378
Reputation
29,020
Reaction score
13,129
Trophy points
1,393
Location
Bochum, Germany
Activity points
283,145
You would want to implement a state machine respectively synchronous edge detection logic and a counter, operated with the 27 MHz system clock.

The obvious way is with two one-shot timers.
There are other obvious ways for it in FPGAs (programmable logic). If you don't know what DE2 is (an Altera FPGA development board), you should notice the forum.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top