odnata
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- Dec 18, 2014
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Hi
When I try a to create a logic net, to connect a power management controller to another component (both written in verilog), I'm not able to see the created net in the schematics view.
The UPF-file were interpreted without any errors (I've also double checked the naming )
The section from the UPF-file:
[...]
set_scope LFSR
create_logic_port WAKE_UP_Domain_2_LFSR -direction in
create_logic_net WAKE_UP_Domain_2_LFSR
connect_logic_net WAKE_UP_Domain_2_LFSR -ports {
PMCDomain_2/WAKE_UP_Domain_2}
connect_logic_net WAKE_UP_Domain_2_LFSR -ports {WAKE_UP_Domain_2_LFSR}
[...]
set_scope /
create_logic_port WAKE_UP_Domain_2_top -direction in
create_logic_net WAKE_UP_Domain_2_top
connect_logic_net WAKE_UP_Domain_2_top -ports { WAKE_UP_Domain_2_top}
connect_logic_net WAKE_UP_Domain_2_top -ports { LFSR/WAKE_UP_Domain_2_LFSR}
[...]
The Commands in Questasim:
vlog -work work -L mtiPA -f <path>compile_rtl.f
vopt tb -pa_upf <path>out.upf -pa_lib work -pa_enable=nonoptimizedflow+highlight -o top_opt -work work +acc -debugdb -novopt -pa_lib work -pa_all -pa_genrpt=pa+de+nv+u -pa_checks=s+ul+umi+i+r+p+cp+t+upc+npu+ugc +cover
vsim top_opt -pa -novopt -pa_lib work -debugdb=<path>/test_file -l rtl.log -wlf rtl.wlf -L mtiPA -pa_highlight -assertdebug -coverage +notimingchecks
I thought that the optimization is fighting against me, but I can't find the problem. I'm using a nonoptimized design flow
I can proove that the upf interpreter does something with the logic lines due to the fact that in the debug-file test_file contains the names of the logic lines (I've only looked it up with grep)
I'm using questasim-10.2c5
I'm thankfull for every hint
John
- - - Updated - - -
Hi,
I've some new informations:
If I try to add components to the Schematics which have some UPF logic stuff in it, I got a errorline:
If I add components without UPF logic stuff everything is allright
John
When I try a to create a logic net, to connect a power management controller to another component (both written in verilog), I'm not able to see the created net in the schematics view.
The UPF-file were interpreted without any errors (I've also double checked the naming )
The section from the UPF-file:
[...]
set_scope LFSR
create_logic_port WAKE_UP_Domain_2_LFSR -direction in
create_logic_net WAKE_UP_Domain_2_LFSR
connect_logic_net WAKE_UP_Domain_2_LFSR -ports {
PMCDomain_2/WAKE_UP_Domain_2}
connect_logic_net WAKE_UP_Domain_2_LFSR -ports {WAKE_UP_Domain_2_LFSR}
[...]
set_scope /
create_logic_port WAKE_UP_Domain_2_top -direction in
create_logic_net WAKE_UP_Domain_2_top
connect_logic_net WAKE_UP_Domain_2_top -ports { WAKE_UP_Domain_2_top}
connect_logic_net WAKE_UP_Domain_2_top -ports { LFSR/WAKE_UP_Domain_2_LFSR}
[...]
The Commands in Questasim:
vlog -work work -L mtiPA -f <path>compile_rtl.f
vopt tb -pa_upf <path>out.upf -pa_lib work -pa_enable=nonoptimizedflow+highlight -o top_opt -work work +acc -debugdb -novopt -pa_lib work -pa_all -pa_genrpt=pa+de+nv+u -pa_checks=s+ul+umi+i+r+p+cp+t+upc+npu+ugc +cover
vsim top_opt -pa -novopt -pa_lib work -debugdb=<path>/test_file -l rtl.log -wlf rtl.wlf -L mtiPA -pa_highlight -assertdebug -coverage +notimingchecks
I thought that the optimization is fighting against me, but I can't find the problem. I'm using a nonoptimized design flow
I can proove that the upf interpreter does something with the logic lines due to the fact that in the debug-file test_file contains the names of the logic lines (I've only looked it up with grep)
I'm using questasim-10.2c5
I'm thankfull for every hint
John
- - - Updated - - -
Hi,
I've some new informations:
If I try to add components to the Schematics which have some UPF logic stuff in it, I got a errorline:
Code:
add schematic -full sim:/tb/TOP
# ShowFullView error1 DebugDB QueryError:
# error3 = near ")": syntax error
If I add components without UPF logic stuff everything is allright
John