Create floorplan each time

[ee1]

Hi,
What is the best way to create the floorplan if i run the asic flow few times for the same design,
Do you recommend creating the floorplan, save it as def and then read the def each time?
Will it save time?

Anonther question regarding floorplan - if i give DC the def file of the design as an input would the synthesis be more efficiant and accurate? So should i run synthesis again after creating the floorplan and go back to synthesis?

Thank

 

[kbulusu]

why do you want to create floorplan every single time if the RTL/macro doesnt change that much..ofcourse this is assuming your initial floorplan you come up with has decent std cell utilization around 0.6 to 0.7..save it as def and read that back in...now whether the synthesis tool will be more accurate, it might but it really depends on the hueristics algorithm and how much floorplan info dct uses...For example, in RTL Compiler from synthesis, there is generate_ple flow which utilizes floorplan info upfront to get the accurate wireload/interconnect info etc and the synthesis optimzations utilize that and thus its very tightly coupled with P&R. Same with their newer tool RCP (RTL Compiler physical). Other vendors like magma also does something similar. But it all boils down to accuracy and how much info does each tool use from def ( fp coordinates, macro pl, pin assignment) etc..

hope this helps..

---------- Post added at 23:46 ---------- Previous post was at 23:44 ----------

why do you want to create floorplan every single time if the RTL/macro doesnt change that much..ofcourse this is assuming your initial floorplan you come up with has decent std cell utilization around 0.6 to 0.7..save it as def and read that back in...now whether the synthesis tool will be more accurate, it might but it really depends on the hueristics algorithm and how much floorplan info dct uses...For example, in RTL Compiler from synthesis, there is generate_ple flow which utilizes floorplan info upfront to get the accurate wireload/interconnect info etc and the synthesis optimizations utilize that and thus its very tightly coupled with P&R. Same with their newer tool RCP (RTL Compiler physical). Other vendors like magma also does something similar. But it all boils down to accuracy and how much info does each tool use from def ( fp coordinates, macro pl, pin assignment) etc..

hope this helps..