#### kaiserschmarren87

##### Member level 4

I have understood what CRC algorithm is. I found enough information online. Also found online tools to generate VHDL code for the specified data and polynomial.

*generated from this webpage:*

**Could someone be generous to explain how the data and crc bits are chosen for CRC generation in this VHDL code*****broken link removed***

Code:

```
-- ########################################################################
-- CRC Engine RTL Design
-- Copyright (C) www.ElectronicDesignworks.com
-- Source code generated by ElectronicDesignworks IP Generator (CRC).
-- Documentation can be downloaded from www.ElectronicDesignworks.com
-- ********************************
-- License
-- ********************************
-- This source file may be used and distributed freely provided that this
-- copyright notice, list of conditions and the following disclaimer is
-- not removed from the file.
-- Any derivative work should contain this copyright notice and associated disclaimer.
-- This source code file is provided "AS IS" AND WITHOUT ANY WARRANTY,
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE.
-- ********************************
-- Specification
-- ********************************
-- File Name : CRC8_DATA16.vhd
-- Description : CRC Engine ENTITY
-- Clock : Positive Edge
-- Reset : Active High
-- First Serial : MSB
-- Data Bus Width : 16 bits
-- Polynomial : (0 2 3 4 8)
-- Date : 16-Jun-2015
-- Version : 1.0
-- ########################################################################
LIBRARY IEEE ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY crc_gen IS
PORT(
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
soc : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
data_valid : IN STD_LOGIC;
eoc : IN STD_LOGIC;
crc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
crc_valid : OUT STD_LOGIC
);
END crc_gen;
ARCHITECTURE behave OF crc_gen IS
SIGNAL crc_r : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL crc_c : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL crc_i : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL crc_const : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
BEGIN
crc_i <= crc_const when soc = '1' else
crc_r;
crc_c(0) <= data(0) XOR data(4) XOR data(5) XOR data(6) XOR data(13) XOR crc_i(5) XOR data(15) XOR crc_i(7) XOR data(10) XOR crc_i(2);
crc_c(1) <= data(1) XOR data(5) XOR data(6) XOR data(7) XOR data(14) XOR crc_i(6) XOR data(11) XOR crc_i(3);
crc_c(2) <= data(0) XOR data(2) XOR data(7) XOR data(8) XOR crc_i(0) XOR data(12) XOR crc_i(4) XOR data(4) XOR data(5) XOR data(13) XOR crc_i(5) XOR data(10) XOR crc_i(2);
crc_c(3) <= data(0) XOR data(1) XOR data(3) XOR data(8) XOR data(9) XOR crc_i(1) XOR crc_i(0) XOR data(14) XOR crc_i(6) XOR data(11) XOR crc_i(3) XOR data(4) XOR data(15) XOR crc_i(7) XOR data(10) XOR crc_i(2);
crc_c(4) <= data(0) XOR data(1) XOR data(2) XOR data(9) XOR crc_i(1) XOR data(12) XOR crc_i(4) XOR data(11) XOR crc_i(3) XOR data(6) XOR data(13) XOR crc_i(5);
crc_c(5) <= data(1) XOR data(2) XOR data(3) XOR data(10) XOR crc_i(2) XOR data(13) XOR crc_i(5) XOR data(12) XOR crc_i(4) XOR data(7) XOR data(14) XOR crc_i(6);
crc_c(6) <= data(2) XOR data(3) XOR data(4) XOR data(11) XOR crc_i(3) XOR data(14) XOR crc_i(6) XOR data(13) XOR crc_i(5) XOR data(8) XOR data(15) XOR crc_i(7) XOR crc_i(0);
crc_c(7) <= data(3) XOR data(4) XOR data(5) XOR data(12) XOR crc_i(4) XOR data(15) XOR crc_i(7) XOR data(14) XOR crc_i(6) XOR data(9) XOR crc_i(1);
crc_gen_process : PROCESS(clock, reset)
BEGIN
IF(reset = '1') THEN
crc_r <= "00000000" ;
ELSIF( clock 'EVENT AND clock = '1') THEN
IF(data_valid = '1') THEN
crc_r <= crc_c;
END IF;
END IF;
END PROCESS crc_gen_process;
crc_valid_gen : PROCESS(clock, reset)
BEGIN
If(reset = '1') THEN
crc_valid <= '0';
ELSIF( clock 'EVENT AND clock = '1') THEN
IF(data_valid = '1' AND eoc = '1') THEN
crc_valid <= '1';
ELSE
crc_valid <= '0';
END IF;
END IF;
END PROCESS crc_valid_gen;
crc <= crc_r;
END behave;
```

I know that the CRC is obtained from the polynomial given from which a Linear Feed Back Shift Register realization will yield the required CRC as shown below (just for example but not specific to the VHDL code given above).

I just need the logic behind XOR operation

*GIVEN IN THAT VHDL CODE*which helps for parallel CRC operation as per the below documents:

1. http://outputlogic.com/my-stuff/parallel_crc_generator_whitepaper.pdf

2. http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.75.387&rep=rep1&type=pdf

I have implemented CRC Generation and Detection from the general XOR operation but it takes more clock cycles. So I had to rely on parallel CRC generation technique.