Aside from the CPU, the memories want different things.
DRAM (optimized for cost) wants trench capacitors or at
least capacitors optimized for areal density. Meanwhile
"VNAND" (or any EE memory) wants an oxide / dielectric
that well tolerates repeated current stress (which normal
reliable FETs would prohibit) and high voltage programming
features, which DRAM and CPU don't need.
You can find technologies with EE features. These could
be used for CPU ("it's just gates") and DRAM (if you can
tolerate the inferior density - SRAM might fit tighter if you
have XXnm FETs, and is likely already supported in flash
memory technologies).
It's not a matter of "can't", it's a matter of competitiveness
(commercial mass market) or customers (heavy freight to
pay, all that up front NRE against a probably limited lifetime
quantity).
Of all the problem s I'd call EE reliability the biggest / most
technology-application-limiting. If you can get access to a
flow that satisfies the nonvolatile retention / wearout issues,
most other "stuff" could be made (perhaps at way inferior
density).
DRAM is so dirt cheap, you'd be mis-spending money to
integrate that on a non-optimized flow, is my opinion. But
lots of people seem to think that "system on a chip" means
"entire system on a chip" and you'll be set. Neglecting such
minor details as multi-rail and dead quiet power supplies,
and how a bazillion transistors talk usefully to the outside
world with no added help.
Given that it doesn't, really, I see little glory in pulling DRAM
onto the die (where you will pay for all the umpteen levels
of fine pitch interconnect it doesn't need or want, and all
the multiple FET species likewise, attending a modern SoC
flow, yet never get the special capacitor you need for
density).
But "by any means necessary", yes you could. Not at the
foundries you've contacted, with the relationship you've
got, I guess.