bigurf
Newbie level 1
coolrunner2 cpld architecture
HI
I have a coolrunner 2 development board. Dividing the clock was easy, I now have 90Hz clock, but the darn buttons just will not be debounced. I have the VHDL code to debounce a MAX FPGA, and the code makes sense, 4 bit shift registry. It compiles but just wont work. I need a help to debounce my push buttons in VHDL for this CPLD. If any one could please tell me how to do that
Thanks.
HI
I have a coolrunner 2 development board. Dividing the clock was easy, I now have 90Hz clock, but the darn buttons just will not be debounced. I have the VHDL code to debounce a MAX FPGA, and the code makes sense, 4 bit shift registry. It compiles but just wont work. I need a help to debounce my push buttons in VHDL for this CPLD. If any one could please tell me how to do that
Thanks.