CPLD Debounce Coolrunner 2, HELP desperately needed

[bigurf]

coolrunner2 cpld architecture

HI
I have a coolrunner 2 development board. Dividing the clock was easy, I now have 90Hz clock, but the darn buttons just will not be debounced. I have the VHDL code to debounce a MAX FPGA, and the code makes sense, 4 bit shift registry. It compiles but just wont work. I need a help to debounce my push buttons in VHDL for this CPLD. If any one could please tell me how to do that

Thanks.

 

[kib]

cpld debounce

hope this helps

LIBRARY IEEE;
USE  IEEE.STD_LOGIC_1164.all;
USE  IEEE.STD_LOGIC_ARITH.all;
USE  IEEE.STD_LOGIC_UNSIGNED.all;

	-- Debounce Pushbutton: Filters out mechanical switch bounce for around 40Ms.
ENTITY debounce IS
	PORT(pb, clock_100Hz 	: IN	STD_LOGIC;
		 pb_debounced		: OUT	STD_LOGIC);
END debounce;

ARCHITECTURE a OF debounce IS
	SIGNAL SHIFT_PB 		: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN

	-- Debounce clock should be approximately 10ms or 100Hz
	PROCESS
	BEGIN
  		WAIT UNTIL (clock_100Hz'EVENT) AND (clock_100Hz = '1');
		-- Use a shift register to filter switch contact bounce
  		SHIFT_PB(2 DOWNTO 0) <= SHIFT_PB(3 DOWNTO 1);
  		SHIFT_PB(3) <= NOT PB;
  		IF SHIFT_PB(3 DOWNTO 0)="0000" THEN
   			PB_DEBOUNCED <= '0';
  		ELSE 
   	 		PB_DEBOUNCED <= '1';
  		END IF;
	END PROCESS;
END a;