counter in opposite direction

[MRFGUY]

I hvae design very simple 2 bit up counter by using Xilinx schematic. I am using Xilinx 7.1i and test bench o/p show correctly(0-1-2-3-0). But when I download to XC9572 cpld it show on 7-seg display as down counter (0-3-2-1). I attached my sch file for your ref.

What's wrong with my sch or any other setting for cpld.

Thanks

 

[echo47]

I have not looked at your file, but check for this bug:
**broken link removed**

 

[MRFGUY]

After sp3 installed, the logic err is just disappear.

I have 1 more question concern with cpld XP9572. Do we really need to connect all 3 pins (10, 23, 31) to ground. During testing I just used 1 pin and one of the output is just disappear. (like counter run 1-2-3-12-3). But test bench Wform is correct.

After I connect all 3 pins to ground and the counter run correctly, shows all nos.

What is the good way most of you guys do. (only 1 leg to gnd and 1 leg to vcc)

 

[sysco_stevens]

you'd better use VERILOG HDL to design your counter,

that is simple and not prone to mistake.

best regards

I hvae design very simple 2 bit up counter by using Xilinx schematic. I am using Xilinx 7.1i and test bench o/p show correctly(0-1-2-3-0). But when I download to XC9572 cpld it show on 7-seg display as down counter (0-3-2-1). I attached my sch file for your ref.

What's wrong with my sch or any other setting for cpld.

Thanks