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COSTAS loop implementation using System Generator tool (ISE)

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demod

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I have developed a simple costas loop for BPSK demodulation. It is working fine for 8Mbps data rate BPSK. The overall sampling freq is 125 MHZ. Inside the loop, the corresponding FIR and loop filters are running at 25 MHz. The lock range achieving is +100 KHz to -100 KHz of centre 30 Mhz.

Now, I am updated the same for QPSK demodulation. The updations included Hardlimited costas loop development, FIR data rates as 21.2257 Mbps, Loop filter lock range as +400 KHz to -400 KHz of centre 70 MHZ.

But, I am getting the proper lock till +-50 KHz only. Why is it happening I am not understanding. Even same when we implemented in MATLAB, we observed till+-100 KHz only lock is coming. So, what parameters are affecting this lock range differently in two domains (sysgen and Matlab).

To implement this, I have used the Xilinx block sets in System generator tool and Matlobe code in Matlab.

Kindly advice, what things I need to cross check to complete my development.
 

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