Where is timing loop in my design?

[Kevsh]

Here is VHDL-code of a simple frequency devision circuit:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity freq_div is
Port ( 
    clk_in: in std_logic;
    div: in std_logic_vector(7 downto 0);
    clk_out: out std_logic
);
end freq_div;

architecture Behavioral of freq_div is
    
    signal cnt : unsigned(7 downto 0) := (others => '0');
    signal ib_div : std_logic_vector(7 downto 0);
    
begin

    ib_div <= div;

    p_div: process(clk_in)
    begin
        if (cnt = unsigned(div)) then
            cnt <= (others => '0');
            clk_out <= '1';
        else
            cnt <= cnt + 1;
            clk_out <= '0';
        end if;
    end process;

end Behavioral;

I received critical warning: [Synth 8-295] found timing loop. I can't find here a timing loop...

 

[FvM]

Missing edge sensitive condition, e.g.

if rising_edge(clk_in) then

Without it, your HDL defines a purely combinational hardware and doesn't synthesize registers. Process sensitivity list is ignored in synthesis.