[SOLVED] Correction required in Verilog Code

UFK · Feb 11, 2011

Dear Verilog Users

Im posting a portion of my code for a compression decoder.
It gives me no syntax error but when i try synthesizing it gives the following error:

INTERNAL_ERROR:Xst:cmain.c:3446:1.47.6.2 - To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com

No matter what i change in the code it still gives the same error.

My code is

module try(clk);

input clk;

integer k;
reg [31:0] rec_img [0:255]; //For reconstructed image

reg Bit_seq1 [0:7];
reg Bit_seq2 [0:6];

initial
begin

$readmemb("Bit_seq1.txt",Bit_seq1, 0, 7);
$readmemb("Bit_seq2.txt",Bit_seq2, 0, 6);

end

always @ (posedge clk)
begin

if (Bit_seq2[k]== 0) //For (0,0)

rec_img[30] =1;

end
endmodule

The test file Bit_seq2. txt is

0
0
0
0
0
0

Please tell me what im doing wrong in my code.

Thanks alot in advance

RBB · Feb 11, 2011

Is $readmemb synthesizable with your compiler? It isn't with any synthesis tools I've ever used,

UFK · Feb 11, 2011

Im using a Spartan 3E Xilinx device and my software version is 11.3. My encoder code uses the $readmemb task and is synthesizing fine. I have no idea what im doing wrong in my decoder code. Im not very good at Verilog so its hard to figure out my mistake.
Thanks for replying

phoenixpavan · Feb 11, 2011

Hi UNK,

Please refer the Xilinx thread INTERNAL_ERROR:Xst:cmain.c:3446:1.47 - Xilinx User Community Forums it had been resolved..i think.

Helpful??

UFK · Feb 11, 2011

Thanks phoenixpavan

I tried the suggestions on that forum and neither didnt work for me (((

phoenixpavan · Feb 11, 2011

Hey UFK,

Try posting a request to the Xilinx customer support...may be they will help you as I think it has got to do something with the tool files.

cheers

[SOLVED] Correction required in Verilog Code

UFK

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[SOLVED] Correction required in Verilog Code

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