UFK
Member level 3
Dear Verilog Users
Im posting a portion of my code for a compression decoder.
It gives me no syntax error but when i try synthesizing it gives the following error:
INTERNAL_ERROR:Xst:cmain.c:3446:1.47.6.2 - To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com
No matter what i change in the code it still gives the same error.
My code is
The test file Bit_seq2. txt is
Please tell me what im doing wrong in my code.
Thanks alot in advance
Im posting a portion of my code for a compression decoder.
It gives me no syntax error but when i try synthesizing it gives the following error:
INTERNAL_ERROR:Xst:cmain.c:3446:1.47.6.2 - To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com
No matter what i change in the code it still gives the same error.
My code is
module try(clk);
input clk;
integer k;
reg [31:0] rec_img [0:255]; //For reconstructed image
reg Bit_seq1 [0:7];
reg Bit_seq2 [0:6];
initial
begin
$readmemb("Bit_seq1.txt",Bit_seq1, 0, 7);
$readmemb("Bit_seq2.txt",Bit_seq2, 0, 6);
end
always @ (posedge clk)
begin
if (Bit_seq2[k]== 0) //For (0,0)
rec_img[30] =1;
end
endmodule
The test file Bit_seq2. txt is
0
0
0
0
0
0
Please tell me what im doing wrong in my code.
Thanks alot in advance