corner simulation for vds greater than vdsat

[amriths04]

corner simulation

friends,
i designed an opamp which works only in tt corner and fails in other 3. so what changes must i make? or must i design it from scratch again? advice me as to what technique i must use in making a design work on all the corners..

thank you,

 

[DenisMark]

adc corner simulation

What does parameters fail? What is ur circuitry?
The first of all check that all mosfets operate in requered regions in this failed corners. U should always check this condition for slow models and high temperature.

 

[sharpsheep]

corners simulation

Hi,
Make sure you simulate opamp with the cmfb circuit and current mirrored bias curcuit. Check the operation region of the tail curret mosfet.

 

[amriths04]

folder cascode

@dennismark
mine is a two stage opamp with first stage double cascode-telescopic and second stage a normal common source. i am clearly able to find that all my transistors left saturation in ss. even when i tried to achieve the spec in ss it fails in tt. that is, it works only in one corner.


@sharpsheep
i used a resistive cmfb circuit for my 2-stage opamp. my first stage is a double cascode telescopic and my 2nd stage is a common source(as usual).

but i used ideal battery bias for giving my gate bias voltages to all the transisitors. i also used an ideal dc current source and mirrored it into the tail of my opamp.

sharpsheep, i designed it at first hand using tt corner and it gave me 80dB gain. but when i ran it in ss, all my transistors left saturation. i biased my tail transistor drain voltage to be 0.6 volts(Vov = 0.1V). i am not sure whether this is enough. please help me by sharing any circuit that you used for biasing the gates.

thank you,

Hi,
Make sure you simulate opamp with the cmfb circuit and current mirrored bias curcuit. Check the operation region of the tail curret mosfet.

 

[DenisMark]

how to test op amp for pvt corners

Biasing by voltage sources this is ur problem!! U should do simulation for circuit with biasing network. Using ideal current source isn't correct for OPAMP simulation and validation. Really current reference changes with PVT and OPAMP paramenters changes too. U need include current reference in simulation too.
Why you use telescopic 1st stage? What is ur ICMR? May u need folder cascode? 80 dB not problem for 2 stage OPAMP in 0.6 um process e.g.
P.S. Better condition for tail transistor is operation in strong inversion when Vov>=0.2V

 

[amriths04]

common source bias corner

denismark,
actually i am designing on 180nm process, for which 80dB gain is really hard to achieve in a single stage. i also needed a BW of 1GHz. but my ICMR requirement was only about 0.01mV as i would be using it in a negative feedback system(for my switched capacitor pipelined adc). so i did not need folded cascode for it's power consumption. here i got my gain to be 400*25 easily and BW of 900MHz.

denismark can i use any arbitary transistor arrangement for biasing the gates and feeding in the reference currents or is there any prescribed technique for that. from your schematic i can see that you had used a bandgap reference sort of biasing with 1m ohm R(why 1m ohm?). can you share the pdf that you read for the biasing technique you had used.

and also can you kindly show me your cmfb part. did you use resistive or switched cap?

thank you,

Biasing by voltage sources this is ur problem!! U should do simulation for circuit with biasing network. Using ideal current source isn't correct for OPAMP simulation and validation. Really current reference changes with PVT and OPAMP paramenters changes too. U need include current reference in simulation too.
Why you use telescopic 1st stage? What is ur ICMR? May u need folder cascode? 80 dB not problem for 2 stage OPAMP in 0.6 um process e.g.
P.S. Better condition for tail transistor is operation in strong inversion when Vov>=0.2V

 

[DenisMark]

common source bias corners

Ok.
"arbitary transistor arrangement"? Not of course It's analog design. Currents in biasing network must be some portion of currents flowing in OPAMP branches. With same ratio the transitors differ. Some transitors for biasing cascode transisitors should be at least 4 times less (difficult indicate at picture). U can read about this in any book for beginers.
Thera isn't bandgap at picture u've been mistaken. But if u need constant GBW i think for diff.pair operated in weak region the PTAT current source is right (GBW=Gm/Cc, Gm=Id/n*Vt, Id=(Ut/R)*ln(N) - PTAT current, where Ut=k*T/q).
1mOhm presistors added only to mix nets with different names.
This is single ended OTA part of comparator. I give it for you only as example.