mike_bihan
Full Member level 3
hey, friends:
I am designing a transmission line pair for CMOS on-chip CML clock routing.
The trade-off is between characteristic impedance, attenuation, crosstalk and others i might ignored yet.
My 2D simulator tells me that I will get a larger Zo for wider seperation between two traces. And I will get lower loss for wider traces. So, comparing two sets of geometric configs:
1. W=3um, Seperation=5um;
2. W=4um, Seperation=8um;
I get larger Zo and lower loss. However, the two lines behaves more like lightly coupled indelendent line. I am not sure that what is going to happen to the 2nd kind of sizing. Who is decideing the maximum spacing between coplanar coupled striplines.
What I can figure out is more EMI issue in 2nd setting. Pls advice and welcome discussion.
many thanks,
I am designing a transmission line pair for CMOS on-chip CML clock routing.
The trade-off is between characteristic impedance, attenuation, crosstalk and others i might ignored yet.
My 2D simulator tells me that I will get a larger Zo for wider seperation between two traces. And I will get lower loss for wider traces. So, comparing two sets of geometric configs:
1. W=3um, Seperation=5um;
2. W=4um, Seperation=8um;
I get larger Zo and lower loss. However, the two lines behaves more like lightly coupled indelendent line. I am not sure that what is going to happen to the 2nd kind of sizing. Who is decideing the maximum spacing between coplanar coupled striplines.
What I can figure out is more EMI issue in 2nd setting. Pls advice and welcome discussion.
many thanks,
