convert vhdl function in to verilog function

[Alka Arora]

Hi ,

I need to convert this VHDL function in to verilog:Could you please help.


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FUNCTION EXT (ARGUMENT: STD_LOGIC_VECTOR; SIZE: NATURAL) RETURN STD_LOGIC_VECTOR IS
VARIABLE RS: STD_LOGIC_VECTOR (SIZE-1 DOWNTO 0);
VARIABLE TMP: STD_LOGIC_VECTOR (ARGUMENT'length-1 DOWNTO 0);
CONSTANT MSB: natural := min(ARGUMENT'length, SIZE) - 1;
BEGIN
TMP := TO_X01 (ARGUMENT);
RS := (others => '0');
RS(MSB DOWNTO 0) := TMP(MSB DOWNTO 0);
RETURN RS;
END;

Thanks