Convert gate level design to transistor level desig

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md_umar

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hi all,
let me know how to convert gate level design to transistor level design for stick diagram.
thanx!\]
 

Hi !!!
If you have the library of standard cells, you will can import your netlist to cadence CIW schematic view!

https://obrazki.elektroda.pl/1_1163435443.jpg

All standard cells have schematic view!!
In the good library !!!!!!
 

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