Convert gate level design to transistor level desig

[md_umar]

hi all,
let me know how to convert gate level design to transistor level design for stick diagram.
thanx!\]

 

[Shurik]

Hi !!!
If you have the library of standard cells, you will can import your netlist to cadence CIW schematic view!

https://obrazki.elektroda.pl/1_1163435443.jpg

All standard cells have schematic view!!
In the good library !!!!!!