raghava216
Junior Member level 3
I want to a compare a variable of type 'genvar' (index used in generate-for loop of verilog) with a 3 bit vector.
Let 'i' is a index variable in generate*statement in both VHDL and Verilog.
In VHDL, this will do
if (i = conv_integer(A(2 DOWNTO 0)) THEN
B <= C;
ENDIF;
What is the equivalent of the above code in Verilog?
Will this work?
if (i == A[2:0])
B <= C;
Pl. help
Let 'i' is a index variable in generate*statement in both VHDL and Verilog.
In VHDL, this will do
if (i = conv_integer(A(2 DOWNTO 0)) THEN
B <= C;
ENDIF;
What is the equivalent of the above code in Verilog?
Will this work?
if (i == A[2:0])
B <= C;
Pl. help