library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity booth_controller is
port (clk , qn , qnprev, count : in std_logic;
load , start, count_en, clr, rshift, add1 ,sub : out std_logic --is START in std_logic or out
);
end booth_controller;
architecture Behavioral of booth_controller is
type state_type is (init, hold, subt, addi, shift, counter, done);
signal sreg, snext : state_type;
begin
process (clk)
begin
if rising_edge (clk) then
sreg <= snext ;
end if ;
end process;
process (sreg)
begin
case sreg is
when init =>
-- here the start state hasn't been defined
clr <= '0' ;
if (start <= '1' )then
snext <= hold;
else
snext <= init;
end if;
when hold => start<='0';
if(load <= '1' and qn <= '1' and qnprev <='0' ) then
snext <= sub ;
else if (load <= '1' and qn <= '1' and qnprev <= '1' ) or (load <='1' and qn <='0' and qnprev <= '0' ) then
snext <= shift ;
else if (load <= '1' and qn <= '0' and qnprev <='1' ) then
snext <= add ;
elsif (load<= '0' ) then
snext <= hold;
end if ;
when subt=> sub <= '1' ;
snext <=shift;
when addi => add1 <= '1';
snext <= shift ;
when shift => add1 <= '0';
sub <= '0';
if (count != '0') then
snext <= hold;
else
snext <= done;
end if ;
when done => if (start <= '1') then
snext <= init ;
else
snext <= done;
end if ;
when others => snext <= init;
end case ;
end process ;
end Behavioral;