Controller for booth multiplier syntax problem

[sarjumaharaj]

Hello, I am designing the controller for booth multiplier. (more info on will be found : BOOTH MULTIPLIER ). You can see the ASM CHART ON THE LINK. However, i've added a few more states like hold and end to it. But leaving the design aside, can anyone please see what is wrong with the code. It shows error near when in multiple number of lines. For now I don't need help with design of the controller just the code syntax. Been stuck here for hours. Please anyone!! thanks.

And I am very new to this group, so I don't know the ins and outs of the group properly so if I'm violating any rule please do tell me. I will positively take your comments and criticism.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity booth_controller is
	port (clk , qn , qnprev, count : in std_logic; 
	load , start, count_en, clr, rshift, add1 ,sub : out std_logic  --is START in std_logic or out
	); 		
end booth_controller;

architecture Behavioral of booth_controller is
type state_type is (init, hold, subt, addi, shift, counter, done); 
signal sreg, snext : state_type; 
begin 

process (clk)
begin 
	if rising_edge (clk) then 
		sreg <= snext ; 
	end if ;
end process;

process (sreg)
begin 
	case sreg is 
	when init =>
							-- here the start state hasn't been defined
							clr <= '0' ; 
							if (start <= '1' )then 
								snext <= hold; 
							else 
								snext <= init; 
							end if;
								
	when hold => 		start<='0'; 
							
							if(load <= '1' and qn <= '1' and qnprev <='0' ) then
								snext <= sub ; 
							else if (load <= '1' and qn <= '1' and qnprev <= '1' ) or (load <='1' and qn <='0' and qnprev <= '0' ) then 
								snext <= shift ; 
							else if (load <= '1' and qn <= '0' and qnprev <='1' ) then 
								snext <= add ;
							elsif (load<= '0' ) then 
								snext <= hold; 
							end if ; 
	
	when subt=>			sub <= '1' ; 
							snext <=shift;

	
	when addi => 		add1 <= '1'; 
							snext <= shift ;
							
	
	when shift => 		add1 <= '0';
							sub <= '0';
							
							if (count != '0') then
								snext <= hold; 
							else 
								snext <= done; 
							end if ;
							
	when done => 		if (start <= '1') then
								snext <= init ; 
							else 
								snext  <= done; 
							end if ; 
	when others => 	snext <= init; 
end case ;					

end process ;
end Behavioral;

 

[imbichie]

Replace the else if with elsif like below
both the lines
elsif (load <= '1' and qn <= '1' and qnprev <= '1' ) or (load <='1' and qn <='0' and qnprev <= '0' ) then
and
elsif (load <= '1' and qn <= '0' and qnprev <='1' ) then

 

[TrickyDicky]

Also, another error: != is not a function in VHDL. "Not Equals" is /=

There are also more subtle errors, that may affect your simulation and implementation.

You are using this style in many places:

if (start <= '1') then

<= is less than or equals. With a std_logic, this means that if start is 'U', 'X', '0', or '1', this condition is true. So this will be removed in synthesis as you're asking if the start bit is '0' or '1'. I think you mean:

if (start = '1' ) then

Please refer to a basic tutorial or VHDL cheat sheet for clearer VHDL implementation. It would catch simple errors like the else if above and the ones I have just mentioned.

 

[seeker_123]

why dont you post what are errors you are getting...?


snext <= sub ; -- herer you may want to write subt i guess because sub is output and snext of state_type
so just replace snext <= subt ;
similar error with
snext <= add ; -- replace add with addi


and
if (count != '0') here there is no operator like !=
try with /=


and you are reading your outputs like load and start which is not allowed with out port