The quantity which can give and idea about circuit's testability is Coverage.. viz Test and Fault coverage. This you can get from any ATPG or DFT synthesis tools
Excuse me for bad english!
how I can measure controllability from a verilog file?
I need a file like this format:
Net controllability observability
1 5 6
2 3 12
Hi, U have to go through, to how to measure controllability and observability. As this measurement is totally depend on the Gate (AND,OR,NOT,NAND etc).
There is some calculation for combinational as well as sequential for measuring controllability and observability.
Than is given in the book named :
VLSI test principles and Architectures for DFT
(Chapter 2)
please see this **broken link removed**
slide 34
in this slide with scoap alg calculate controllability and observability for combinational example.
I need a tool that can calculate this numbers.
I know tetramax can calculate this, but it is commerical tool. and I need a free tool.
Controllability and Obserability meaning is DFT.DESIGN FOR TEST(a program to test the design) Which is added in design in synthesis.
And after Fabrication Chips are checked by DFT in ATE(AUTOMATIC TEST EQUIPMENT) to reduce the time of testing and shipping of chips.