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# controllability and observability improvement by scan design

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#### shikharmakkar

##### Junior Member level 1
Hi,
I am studying the basics of dft techniques and is able to understand the basic definitions of controllability and observability in context of testing. What I am not being able to understand is how does adding scan design improves the testability, that is controllability and observability? How the inputs are controlled and the outputs are observed and faults detected? Please help me with this and if possible, explain through waveforms/timing diagrams wrt various clocks and modes of operation like normal, shift and capture. Thanks

you'd better read more about difference between combinational testing vs sequential circuit testing. Why sequential testing is more difficult. The main aim of scan design is to transform sequential testing -> combinational testing, which make the test easier.

you'd better read more about difference between combinational testing vs sequential circuit testing. Why sequential testing is more difficult. The main aim of scan design is to transform sequential testing -> combinational testing, which make the test easier.

can you explain how it's behaving as a combinational circuit? Can you provide me with some waveforms or resources?

Hello,

You just need to clear the basics questions like Why DFT and How DFT works?
First step for scan is convert as many as much possible from the normal flop to scan flop.
After converting the scan flop and done the scan stitching, all flops are working as a shift register in shift mode.
Now, in shift mode we can shift the whatever data we want to shift in the scan flop. Now main target is to cover the combinational logic in between two consecutive scan flops. So after shifting, we have a control of combinational logic as combo logic input coming from flop output and there after moving to capture mode we can capture the output of combinational logic in the scan flop and do the shift out the captured data. In such a way we have a higher testability by converting the normal flop to scan flop.
Hope it helps.

Hi,

Refer a book named "VLSI Test Principles and Architectures". It is a basic level book for DFT newbies.It helps me a lot. You will definitely find your answer.

Here is my perspective, controllability and observability are the keys to achieve an Easy-to-test design. In complex designs controlling a deeply embedded node from PIs and observing the same node at the POs is a difficult thing. Difficulty is due to the fact that there will be huge number of sequential elements between such a node and PIs/POs. Whenever there are sequential elements you will have to generate patterns keeping in mind the clocking scenarios of different sequential elements (Sequential ATPG). It is possible, but highly resource consuming. Combinational ATPG makes it easy by converting all flops in scan-enable flops. Now every flop is accessible from the top in a shift register manner (Understand the sequence of Combinational ATPG). Now the deeply embedded combinational logic will be fed by scan-enabled flops which will be acting as Pseudo PIs/POs.

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