Continuous time comparator (Systematic offset)

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diezclos11

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I am developing a continuous time comparator for a single-slope ADC. My comparator is a 5t ota with pmos inputs and followed by a cs stage with a current source load (nmos input). For my particular application, I would like to avoid using auto-zero as I can cope with the random induced input offset. However I would like to develop the design to minimize the affect of input referred systematic offset. Any tips on this design? I am also trying to choose the sizing of the different transistors based on the GM/ID method.
 

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Are you saying you want to correct offsets which have a
source external to the comparator?

Correcting a continuous-time comparator might need you to
ping-pong a pair of autozero comparators, use one while
zeroing the other. But autozero tends to have a lower frequency
bound, set by bleed-out of the "trim memory" capacitor(s)
against leakage terms, so then you can't just ping-pong by
clocking on output transitions or like that, if input signal of
interest is quasi-DC and sparsely triggering if at all.
 

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