A
ahmadagha23
Guest
Hi,
1- Can I specify the mapped package pins for ports in VHDL code only in .UCF file? can you write its instruction and the steps of adding this file to my design? Is it possible to implement my design and configure my FPGA board without declaring any .ucf file?
2- what is the difference between synplifypro and ise constraints?
regards
1- Can I specify the mapped package pins for ports in VHDL code only in .UCF file? can you write its instruction and the steps of adding this file to my design? Is it possible to implement my design and configure my FPGA board without declaring any .ucf file?
2- what is the difference between synplifypro and ise constraints?
regards