library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity top is
port
(
CLK : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
attribute PERIOD : string;
attribute PERIOD of CLK : signal is "50 MHz";
attribute LOC : string;
attribute LOC of CLK : signal is "C10";
attribute LOC of Q : signal is "E1 E2 E3 E4";
end top;
architecture archi of top is
signal tmp: std_logic_vector(3 downto 0) := "0000";
begin
process (CLK)
begin
if (rising_edge(CLK)) then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;