Constraints in a design

DocIng said:

Every port, bus, clock, subdesign and constraints are stored as virtual foldersaccessible from RTL Compiler command window.
the top level input ports are stored in /designs/TOP/ports_in
clkin will be connected to CLK input of TOP module
get_pins /designs/TOP/ports_in/CLK cannot find any pins.

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DocIng said:

I used RTL compiler from cadence.
define_clock -period 100000 -name clkin /designs/TOP/ports_in/CLK

Error : A required object parameter could not be found. [TUI-61] [path_group]
: An object of type 'instance|external_delay|clock|port|pin' named '' could not be found.
: Check to make sure that the object exists and is of the correct type. The 'what_is' command can be used to determine the type of an object.

I dont undesrtand the problem.

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kannanunni said:

Try this : define_clock -period 100000 -name clkin [get_clocks CLK]

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