Hm... It seams to me that electrons move faster in the higher voltage... Am I wrong?Best (fastest) PVT is {process: fast, voltage: low, temperature: low}
What does it exactly mean that the process is "fast" or "slow"?
Not at all, oratie, thank you for sharing your knowledge!Too complicated?
Yes, in the case if you see setup violation in best-case analysis, most likely (somehow not absolutely) a worse setup violation of the same path can be found in worst-case analysis. This is true for hold violations too.Is it possible that the setup violations occur in the best-case analysis (min delays) and hold violations in the worst-case analysis (max delays)?
You can generate a library to represent the analog blackbox & have the timing requirement there. There should be some library generation tool available, which I am not familiar with...How should be handled black boxes in the RTL during the synthesis? Let's say I have a Black Box in my Netlist, which represents an analog module. There are requirements on the timing for its inputs and outputs. How should I implement this timing in the synthesis/sta scripts? Again, this block box is inside another code and does not have its own ports in the top-level.
Thank you in advance for any comments
It might have to do with the switching speed. Sorry for not able to explain, I'm afraid I've forgotten a lot of these basics...Hm... It seams to me that electrons move faster in the higher voltage... Am I wrong?
What does it exactly mean that the process is "fast" or "slow"?
Suggest to run OCV on at least 2 PVT corners: best-case & worst-case. You can either have 2 different libraries for the best & worst PVT corners (need to characterize 2 different libs) or use derate on a single lib (less accurate).Should I define the corners more explicitly (not just by setting -min_delay or -max_delay)?
Not at all, oratie, thank you for sharing your knowledge!
But, for the STA checks (if I remember correct) we just define -min_delay or -max_delay without any consideration in the PVT or RC corners. It seams we suppose that the tool (PrimeTime) is able to take the right parameters from the provided vendor's libraries and RC extraction files. It seems we are missing something... What we are missing? Should I define the corners more explicitly (not just by setting -min_delay or -max_delay)?
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