Constraints for PVT corners

[beowulf]

Hi,
Can somebody point me to some document/book/writeup that explains
1. Basics of PVT corners
2. how to write constraints in DC for different PVT corners....

I have found some good posts related to (1) above but need some more material for setting up the constraint file.

Thanks,
Beo

 

[pavanks]

Sorry that is not that easy to explain in a book.
It requires lot of understanding of the design ur working with prior experience.

 

[beowulf]

I know it cant be found in a book and thats precisely the reason why I am posting it here. Any writeup or sample constraint files will help.
say for a ffhl or ssll/h conditions...

 

[ivlsi]

How many PVT corners do exist? How do they might be defined?

 

[birdy123]

Hi,

Please check the following links it might Help you. I am agree with Pavan that its not that easy to explain in the simpler way. A lot of basics are required.. Still Worth reading these articles.

https://vlsi-expert.blogspot.in/2012/02/parasitic-interconnect-corner-rc-corner.html
https://vlsi-expert.blogspot.in/2012/02/design-constraint-maximum-transition.html
https://vlsi-expert.blogspot.in/2011/02/process-variation-effects-on-design.html

 

[ivlsi]

Recently I was asked "What is Best and Worst PVT?"... So, what's the answer?

 

[birdy123]

Hi Dmitryl,

See as such there is nothing specific Best /Worst PVT. Means it depends on design , so you cann't say that this particular PVT corner is best/worst. So the concept behind is like this..
Lets suppose that you have 100 paths in your design, so it may be possible that 50paths are generating worst result with respect to PVT corner1 and rest of the 50Paths are generating worst result w.r.t PVT corner2. So in this case both the corners are worst corner for that design. That's the reason you can see that during signoff , most of the designer verify the timing in different corners. And they want to make sure that at the end of the day , chip should work in all the worst scenerio.
Same thing is for best case also.

I hope you got my point. But still if you have any confusion, feel free to ask.

Best of Luck.

 

[childs]

Hi,
Normally Best/Worst PVT means the Fastest/Slowest operating condition of the circuit: typical Best (fastest) PVT is {process: fast, voltage: low, temperature: low} while Worst (slowest) PVT is {process: slow, voltage: high, temperature: high}.
However, recent technology process encounters inverse temperature effect, where cells might function faster at certain high temperature than low temperature (example as mentioned during 2007 here: **broken link removed**) Thus it is suggested that you consult with the cell library provider on what PVT is fastest & slowest.

 

[ivlsi]

Is it possible that the setup violations occur in the best-case analysis (min delays) and hold violations in the worst-case analysis (max delays)?

---------- Post added at 11:16 ---------- Previous post was at 11:10 ----------

How should be handled black boxes in the RTL during the synthesis? Let's say I have a Black Box in my Netlist, which represents an analog module. There are requirements on the timing for its inputs and outputs. How should I implement this timing in the synthesis/sta scripts? Again, this block box is inside another code and does not have its own ports in the top-level.
Thank you in advance for any comments

---------- Post added at 11:26 ---------- Previous post was at 11:16 ----------

Best (fastest) PVT is {process: fast, voltage: low, temperature: low}

Hm... It seams to me that electrons move faster in the higher voltage... Am I wrong?
What does it exactly mean that the process is "fast" or "slow"?
Thank you!

 

[oratie]

What does it exactly mean that the process is "fast" or "slow"?

process=fast means, the transistors on the fabricated chip will be fast. The foundry may guarantee, that parameters of transistors (like channel length etc) will be in the predefined window. It means, thet from one chip (wafer) to another chip (wafer) with the same design, the parameters of transistors will be different. The min and max of these parameters are known. The process fast means, that all transistors on the chip have combination of parameters which gives the minimum cell delay.

Also, you should know about RC corners. The width and thickness of wires (metal) are also may vary from chip to chip (even on one chip ). So, for the setup check, you should use RCworst corner for extraction and one of PVT corners that gives you the max cell delay. Too complicated?

 

[ivlsi]

Too complicated?

Not at all, oratie, thank you for sharing your knowledge!

But, for the STA checks (if I remember correct) we just define -min_delay or -max_delay without any consideration in the PVT or RC corners. It seams we suppose that the tool (PrimeTime) is able to take the right parameters from the provided vendor's libraries and RC extraction files. It seems we are missing something... What we are missing? Should I define the corners more explicitly (not just by setting -min_delay or -max_delay)?

Thank you!

 

[childs]

Is it possible that the setup violations occur in the best-case analysis (min delays) and hold violations in the worst-case analysis (max delays)?

Yes, in the case if you see setup violation in best-case analysis, most likely (somehow not absolutely) a worse setup violation of the same path can be found in worst-case analysis. This is true for hold violations too.

How should be handled black boxes in the RTL during the synthesis? Let's say I have a Black Box in my Netlist, which represents an analog module. There are requirements on the timing for its inputs and outputs. How should I implement this timing in the synthesis/sta scripts? Again, this block box is inside another code and does not have its own ports in the top-level.
Thank you in advance for any comments

You can generate a library to represent the analog blackbox & have the timing requirement there. There should be some library generation tool available, which I am not familiar with...

Hm... It seams to me that electrons move faster in the higher voltage... Am I wrong?
What does it exactly mean that the process is "fast" or "slow"?

It might have to do with the switching speed. Sorry for not able to explain, I'm afraid I've forgotten a lot of these basics...

Should I define the corners more explicitly (not just by setting -min_delay or -max_delay)?

Suggest to run OCV on at least 2 PVT corners: best-case & worst-case. You can either have 2 different libraries for the best & worst PVT corners (need to characterize 2 different libs) or use derate on a single lib (less accurate).

 

[oratie]

Not at all, oratie, thank you for sharing your knowledge!
But, for the STA checks (if I remember correct) we just define -min_delay or -max_delay without any consideration in the PVT or RC corners. It seams we suppose that the tool (PrimeTime) is able to take the right parameters from the provided vendor's libraries and RC extraction files. It seems we are missing something... What we are missing? Should I define the corners more explicitly (not just by setting -min_delay or -max_delay)?

You may use set_min_library command in DC or PT (Sets the library to be used for minimum delay analysis). Regarding different RC data, you may consider multi-scenario possibility of tools (where for each scenario you define different libraries, different RC files ...). Or, the simplest way, in one tool session you are reading min libraries and min RC files and doing min_delay (hold) analysis. In the other session, you will load max (worst) libraries, max RC and calculate max_delay (setup).

 

[ivlsi]

How is it possible to checks the netlist with the min_delays on the data path and max_delays on the clocks (worst case for the hold timing checks)?
Is it possible to extract RC delays on the clock trees separately from the RC delays in the nets? I mean to have separate timing files for the Clocks and Data paths? If not, how is it possible to do worst case hold timing checks (min_delays on the data path and max_delays on the clocks)?
Thank you!

---------- Post added at 21:23 ---------- Previous post was at 21:22 ----------

As for the Voltage in the PVT definition... Does it refer to the Vcc (Vdd) or threshold (Vt) voltage?
Thank you!

 

[sam536]

How is it possible to checks the netlist with the min_delays on the data path and max_delays on the clocks (worst case for the hold timing checks)?

<SAM>: Delay is dependent on input slew of the pin. while calcualting the min delay, tool will pick the fastest slew and calculate delay and vice versa. You dont need to two different files to check these cases. SPEF will take care of this issue.

EDA tools may not support directly. Customized scripts can write to generate clock tree RC information as well as data path RC information with attributes if really required. But, I assume your question is simple. with the basics in place, how tool will understand. Tool is tuned to find the delays to calculate min and max delays according to your commands.

Regards, Sam