Constraints for input and output ports at synthesis stage

[Jennis]

Can you please share how do you decide the constraints for input and output ports. Usually it is 20-30% of clock periords but do we really require these constraints if you are doing the synthesis at the chip-level not in block level.

It is also depend on the application but if the design arcehitecture does not have those information then how would designer set those constraints.

Thanks

 

[chipmonkey]

Even if you are doin a chip level synthesis, you will have external designs that interact with your design. Hence it is required to meet timing for this path ie.
reg of external design -> o/p pin of external design -> i/p pin of your design -> reg in your design.

The constraint values are determined from from previous design experience or rough estimations.

 

[Jennis]

I am agree with you. This is what I was doing at the synsthesis level. I was setting 10% of clock period for input and output delay. Timing was passing in Prime-Time. But at the layout stage timing was failing and PD people asked me to justify this timing constraints. Finally I had to remove all my input/output delay constraints from SDC for final sign-off run. So even if you know these constraints are required , sometime you need to remove when you do not have any proper reason. How do you convince others if they do not agree with this .

Thanks